With the development of semiconductor process technology, more and more transistors are integrated into a single chip. As consequence, Integrated Circuits (ICs) can now host more functionality on one chip, leading us to the System-on-Chip (SoC) era. Today SoC is prevalent in all kinds of electronics systems. From embedded systems to cloud computers, SoCs are being used in various configurations for a versatile type of tasks. SoCs are hardware/software systems that integrate variously
hardware components such as memories, peripherals, hardware accelerators, and analog components through an interconnect, with complex software running on the CPU.
The multiple advantages such as robustness, cost, power, size and weight provided by SoCs come with some drawbacks, the most important being the complexity and reliability. The growing class of complex applications such as machine learning and image processing makes it difficult for engineers to close the increasingly severe productivity gap that arises from the integration of hardware and software. The complexity challenge can only be tackled by well-trained engineers with good understanding of the requirements and challenges at all levels of the design process. The main barrier in this regard are: 1) the lack of hardware/software skills, 2) the verification “hell” and 3) the advent of new challenges such as security and reliability that further complicate the optimization efforts. The classic “over-the-wall” approach the design of hardware/software systems is still prevalent, mainly because of the lack of curricula that promote the integration of hardware and software as a single discipline.
The goal of this course is to provide the fundamentals of designing system-on-chip, from the high-abstraction level and refine it down to the implementation. The course will discuss and practice the various state-of-the-art languages and tools used in the industry. Course content is built around a complex SoC-Project (RC car with embedded FPGA, camera, and ultrasound sensors) that students will design, from the high-abstraction level using SystemC TLM and implement in the target FPGA-Platform.
Dr. Christophe Bobda, firstname.lastname@example.org,
352 294 2024
Office Hours: TBD
Join URL: TBD
Teaching Assistant/Peer Mentor/Supervised Teaching Student
Please contact through the Canvas website
- Supervise Teaching Students:
- TLM-Driven Design and Verification Methodology, Brian Bailey, Felice Balarin , Michael McNamara, Guy Mosenson, Michael Stellfox , Yosinori Watanabe, Publisher: lulu.com; 1ST edition (July 20, 2010), ISBN-10: 0557539064, ISBN-13: 978-0557539062
- ESL Design and Verification: A Prescription for Electronic System Level Methodology. Grant Martin, Brian Bailey, Andrew Piziali. Publisher: Morgan Kaufmannl; 1st edition, March 9, 2007 ISBN-10: 0123735513, ISBN-13: 978-0123735515
- Bashir M. Al-Hashimi (Ed.) , “System On Chip: Next Generation Electronics ”, Institution of Engineering and Technology (January 31, 2006)
- A Practical Approach to VLSI System on Chip (SoC) Design, A Comprehensive Guide – Veena S. Chakravarthi, Hardcover ISBN 978-3-030-23048-7, Softcover ISBN 978-3-030-23051-7, Springer 2020
- SystemC-TLM: http://www.accellera.org/
- Introduction: Trends in Computer Systems, SoC definition, benefits, challenges, Class objectives, syllabus, discussions
- SoC Components: Processing (CPU, Accelerators, IPs), Memory and peripherals, On-chip interconnect, Homework (OpenCV tutorial + virtual hardware integration)
- SoC-Implementation (ASIC, FPGAs): FPGA overview and System on FPGA with Xilinx/Intel, VLSI design overview
- OS & Software Integration: OS Basics, resource management, multithreading, Linux installation and configuration on a FPGA SoC
- System-Level Design: Models of computation, SystemC overview, Transaction-Level Modeling (initiators, transactors)
- SoC Verification: Overview of verification techniques, Verification flow, Verification tools (UVM, SCV), Case Studies
- SoC Security: HW/SW Multi-Level Security, Overview of hardware security, IP protection, Encryption, etc…
- Final Project: Design of a camera-based autonomous RC-Car in group of up to 5 students
Evaluation of Grades
- Homework will be mix of fundamental design problem and small project to practice concepts and tools presented in the class.
- Class participation is assess using random quizzes.
- The final exam will be provided in paper form and will cover the core concepts learned during the semester.
- The final project will use a RC car with embedded FPGA, camera, and ultrasound sensor. Students will use this platform to design an application, from the high-abstraction level using SystemC TLM and implement in the target FPGA-Platform.
- The final project will be conducted in a group of 4-5 students. Students will designate a leader in each group who will oversee the division of work. Each student will document his contribution to the project and will be graded accordingly.
- Project work will be equally distributed among participating students. The assessment of individual students in a group project will be done according to the level of participation of each student.